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The Implementation Of Video Coding System By FPGA

Posted on:2017-02-03Degree:MasterType:Thesis
Country:ChinaCandidate:X J WangFull Text:PDF
GTID:2308330482989752Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
Digital video becames more and more widely use, and have penetrated into all aspects of industrial production, daily life, military operations and other field to provid public safety protection. Video coding technology ?s outstanding advantages in terms of stability, functionality, cost, scalability, and other aspects make it important to academic and practical. Video encoding system has a large number of computing. Embedded processors based on the traditional system, such as coding performance, video quality, real-time aspects are unable to meet the increasingly high coding requirements; using video encoder chip or digital signal processor platform coding system, although there are relatively improve coding system performance, but the definition of the platform interface has been cured; and strong based on programmable FPGA platform design video coding scheme, coding is not only high performance and scalability. A large number of domestic and foreign literature shows, FPGA Design and implementation of video coding system can greatly improve the performance and stability of the systerm.This paper in depth study of the H.264 video compression standard, combined with the characteristics of N ios processor and FPGA designs a SOPC system with baseline of H.264 video encoder scheme. First of all, depth study of the theory and its key technology of H.264 encoding, mainly including: 4×4 intra luminance prediction module, 8×8 intra chroma prediction module, 16×16 frame brightness prediction module, 4×4 integer DCT transform module, quantization module, 4×4 inverse integer DCT transform, inverse quantization module, CAVLC entropy coding module, and to filter module. Through the H.264 encoding systerm framework established by the official analysis, removing the high complexity of coding algorithm and little influence of the algorithm module of the systerm, sort out a set H.264 encoding systerm which can be applied in the FPGA.First, in the SOPC Builder development environment, design and build SOPC hardware platform, the main job is to call the SOPC Builder IP core resources and customize the SD Card Controller IP core. Then, the H.264 encoding algorithm was added to NiosⅡ development environment, using C language design the appropriate hardware and software interfaces. Finally, the H.264 encoding algorithm integrated into the SOPC hardware system. And use the H264 visa software to analyze the encode performance.
Keywords/Search Tags:H.264 encode, FPGA, SOPC, NiosⅡ
PDF Full Text Request
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