Design Of Sample And Hold Circuit Of 12-bit Pipeline ADC

In the modern integrated application systems, along with the rapid development of digital signal processing technology and the level of integration process, the So C(system on chip) has played a significant role in many fields which contain the graphical modeling, audio and video, and communication system. Although most of the chips are based on digital logic processing, the analog modules on So C are mainly used in the signal conversion, and most of them are ADC modules which become more and more important. The performance of the ADC module often becomes a bottleneck which restricts the overall performance of a chip. So the in-depth study of ADC module has great application value.Pipelined architecture is selected for the ADC design in this dissertation,and this structure has good speed and accuracy performance as well as the advantages of low power consumption and the reasonable chip area. The design of the sample and hold module of the ADC is a top priority. This dissertation will focus on the design of the sample and hold circuit for the pipeline ADC. This dissertation introduces the research status of the sample and hold circuit and analyses the significance of improving the performance of this circuit in pipeline ADC. The dissertation also exhaustively analyses the design ideas of the entire sample and hold circuit, and gives the specific circuit design process corresponding the index.In this research, the circuit design is based on SMIC 0.18 μm CMOS mixed signal process. Main mission is to complete the design of the sample and hold circuit which includes the operational amplifier module, the switch module, the two-phase non-overlapping clock module and the associated bias voltage module.The simulations of the circuit and layout have been completed, and the overall layout has been optimized.The simulation results of the whole ADC circuit show that the sample and hold circuit can work at the sampling frequency of 40 MHz and can achieve the logic functions correctly. When the frequency of input signal is 10 MHz,effective number of bits(ENOB) can reach 11.3 bit. So the design achieves the requirements of high speed and accuracy, and meets the initial design goals.