Design Of Two Order Of All Digital Phase Locked Loop Based On FPGA

With the rapid development of integrated circuit technology, PLL due to its unique and excellent performance has been widely used. PLL has become a very important module circuit in integrated circuit plays an important role in the overall electronic products. All digital phase locked service compatibility issues of traditional PLL in the production of process. Lock time of the high order PLL make short and the capture of wide range and so on. So the study of high order all digital phase locked loop has a positive and practical significance.The locking time is one of the main dynamic performance of PLL. Although improving its method has many kinds, it is usually used to enhance the order of PLL. However, increasing the number of order of PLL, will increase the number of order of loop filter which bring the problems of complex filter of design. This paper proposes a method for high order all digital phase locked loop by used to integrate of simple first order PLL. Thus it will be avoid the design of complex filter. First of all, the structure and principle of the phase locked loop has been analysised and comparised. According to the design characteristics of the FPGA of module and hierarchy, the phase locked loop is divided into four basic modules, then using Verilog HDL to complete the four modules of the program. It be carried on the comprehensive, functional simulation and timing simulation by using of Xilinx ISE software. If the result of simulation is correct and feasible, the module transfer to all digital phase locked loop. Then the first order all digital phase locked loop will be synthesized and functional simulation and timing simulation.Finally, the two order all digital phase locked loop will be integrated in two all digital phase locked loop which simulate feasible. Then using timing simulation and generating a bit stream file, download to FPGA experimental circuit board to test, which get a satisfactory result.