The Design Of An Automatically Variable Modulus ADPLL

The design and applicatio n of phase-locked loop is the focus of attention in thefie ld of feedback control technolo gy today, phase-locked loop has pla yed a veryimportant and uniq ue role in variety of applications. such as the radar, measure ment,communications, etc. All-d igita l phase-locked loop has its unique advantages. Itsstructure is varied, but short capture time, s mall s ync hronization error, excelle ntanti-interference ability is the standard measure of performance of a phase-lockedloop. On the basis o f reading a lot of DPLL techno logy literature of do mestic andabroad, this artic le summed up the present situatio n and the develop ment leve l ofphase-locked loop technolo gy, analys is the basic structure and princ ip le of a ll-digita lphase-locked loop in-depth, des igned a quick all-digita l phase-locked loop withhigh-precis ion auto matic control mode by us ing Verilog langua ge and top-downdesign approach.The designed all-digita l phase-locked loop cons ist phase detector, digita l filter,digitally controlled oscillator, freque ncy divider circuit and automatic control c ircuit.Amo ng the m, the phase detector made by D flip-flop，the digita l filter is composed byreversib le counter, d igitally contro lled oscillator based on pulse subtraction c ircuit o fa state machine, auto matic contro l c ircuit is set b y the time the d igita l convers ioncircuitry. Compared with the general a ll-digita l phase-locked loop, the design jo inedthe automatic control module, which helped ease the contradictio n between the digita lfilter results a nd all-digita l PLL lock time. The improved digita lly contro lledoscillator has shorten the lock time through the " first coarse the n fine tune ".Each module o f the designed all-digita l phase-locked loop in the artic le has beencode described, comprehens ive and functiona l s imulated. Under the premise of eachmodule can be functiona l simulated, the artic le described the who le circuit withVerilo g hardware langua ge, then functio na l simulation by us ing Models im6.4a andintegration with Quartus11.0. Functio nal s imulation results show that tak ing divis ionfactor N=32and the syste m clock freque ncy is27MHz, the lock time of the all-digita lphase-locked loop is5.3us.