Research On Spurious Supression And Locking Auxiliary Circuit For All-Digital PLL

With the development of wireless communication technologies, more and more products need to be compatible with different communication protocols, which need wide band PLL (phase-locked loop). In recent years, CMOS technology develop quickly, whick improve the number of transistors in unit area greatly and reduce the supply voltage. The performance of ADPLL (all-digital phase-locked loop) now is comparable with analog PLL. ADPLL can speed up the circuit design for automation process of digital circuit, and easy to integrate other digital auxiliary circuits. This thesis mainly studied the nonlinearity of TDC (time-to-digital converter) introdused spur and PLL lock assistive technologies, and propose the corresponding solutions.Firstly, this thesis describes the principle of PLL, and then describes counter and TDC(time to digital converter) in the ADPLL in details. The thesis focuses on the nonlinearity of TDC introduced spurious tones in ADPLL and spurious suppression algorithm. In order to supress spurious tones under different frequencies, we propose an span adjustable variable delay element. For the porpose of speed up PLL locking, we use a binary search algorithm which can narrows the error between the DCO (digitally ontrolled oscillator) output frequency and the target frequency quickly and accurately. In this thesis, we also propose a calbri algorithm which can eliminate the glitches on the output of counter synchronizer.All the circuits are designed in TSMC0.13μm CMOS process. The simulation results show that all the circuits work correctly.