Mixed Signal Correction Interwoven Pipeline Adc Sampling Clock Offset Time

High-performance hybrid integrated circuit is a common key technology to support the new generation broadband wireless communication system. With the rapid development of digital technology, digital signal processing technology is widely used in communications, computer, instrument and other fields. New generation of broadband wireless communication systems require broadband, high-speed, high precision and low power technologies, which makes hybrid integrated circuit, especially high-speed high-precision analog-to-digital converter (ADC), becomes the technical bottleneck of the system application.When a single ADC has reached the limits of existing design conditions and process conditions, in order to break the constraint of conversion rate, parallelization is an effective, or even the only way. With each channel ADC (Sub-ADCs) sampling the input alternately, this ADC implementation is called time interleaving structure.There are various non-ideal factors existing among ADC channels, such as offset mismatch, gain mismatch, bandwidth mismatch and sample-time error, which generate additional spurious distortion, limit the accuracy of the ADC. In particular, sample-time error between channels has seriously hampered the performance of the ADC, becoming the focus of academia and industry research.In this paper, on the basis of analyzing sample-time correction methods, a mixed-signal calibration method is presented to eliminate sample-time error in TI ADCs. A voltage-controlled bootstrapped sampling switch is proposed for error correction. Avoiding the clock jitter of DCDE and the extra cost of calibration logic when using FIR filters, the proposed scheme achieves higher accuracy and efficiency in calibration.The mixed-signal calibration scheme was successfully used in a high performance two-channel time-interleaved14-Bit,200-MSps ADC. Test results show that:correction eliminates the influence of sample-time error on the performance of the whole ADC. The ADC system achieves a typical14-Bit resolution with ENOB improved by more than3Bit, reaching to11.5Bit, and spurious-free dynamic range (SFDR) increased to90.6dBc for more than30dB improvement.