Research Of Digital Calibration Techniques For High-speed Time-interleaved ADCs

Analog-to-Digital Converters(ADCs)are the links that connect the analog world and the digital world,and they play a key role in many areas,such as modern communications,image acquisition,medical electronics and so on.With the rapid development of CMOS technology,the smallest size of the device is scaled down,which brings to the increase of working speed and the decrease of chip area.However,the non-ideal effects of analog circuits are more and more obvious which is due to the decrease of power supply voltage and the drop of transistor intrinsic gain.The speed and accuracy performance of the analog-to-digital converters has tended to be within the physical limits of existing conditions.Time-interleaved ADC(TIADC),which is realized by distributing analog-to-digital conversion operations using multiple ADC channels,is a high-speed and high-precision ADC which can solve high-speed and high-precision contradiction effectively.Now high performance ADCs are almost using this architecture.However,due to the variations in manufacturing process,the mismatches between ADC channels will severely reduce the dynamic performance of the TIADC,and they are offset mismatch,gain mismatch and time mismatch.The effect of a strict analog matching design on the sub-channel ADC achieves little,and using digital calibration-techniques to achieve the elimination of error has become the current mainstream of high-speed TIADC design.They can fully use of the advantages of low power consumption,high reliability,good flexibility of digital circuits.In this paper,blind adaptive full-digital calibration techniques for high-speed time-interleaved ADCs are studied.First of all,theoretical analysis and validation of the impacts on time interleaved ADC channel mismatch errors is achieved through system-level modeling;secondly,based on the research and analysis of the advantages and disadvantages of calibration technology in China and abroad,this thesis presents two calibration digital calibration techniques,and they have been verified from the behavior level;thirdly,the circuit level design is achieved by building the corresponding circuit-level verification platform,and the experimental results further prove the validity and superiority of the calibration algorithms.Specific research works are as follows:Firstly,an adaptive calibration algorithm based on statistics is proposed.The basic idea of the statistics calibration algorithm is that the output average energy of each channel will be consistent since each channel of TIADCs samples the same input signal,and therefore the energy deviation directly reflects the bias error of the system.For offset mismatch and gain mismatch errors,an cascoded calibration algorithm based LMS iterative adaptive calibration algorithm with its own channel is proposed to estimate and compensate the errors,and the introduction of the index average is to improve the accuracy of convergence.For timing mismatch error,we use the average energy characteristics and autocorrelation characteristics of signals to estimate the mismatch errors,and then take advantage of an improved Farrow structure fractional delay filter to compensate the errors.The entire calibration algorithms are implemented in the digital domain.It has simple structure,so the hardware implementation is relatively easy,and can be extended to arbitrary number of channels.Secondly,a novel adaptive calibration algorithm based on signal modulation is proposed.By analyzing and determining the position of the distortion error frequency,we use the method of signal modulation to build a signal with the same frequency as the distortion spectrum,and then compensate the influence of the distortion error by direct reduction.This calibration algorithm can realize a gain mismatch and timing mismatch calibration simultaneously.Further,we use an exponential smoothing filter to smooth the convergence curve which will effectively improve the calibration accuracy and convergence rate.The proposed calibration algorithm has a comparative advantage in the calibration effect and the cost of hardware.The proposed calibration technique can effectively calibrated the Nyquist input signal(except for special individual frequency points)within the band.Compared with those existing algorithms,the proposed calibration algorithm has a greater advantage on calibration effect and hardware resources.Thirdly,a 12-bit 100MS/s pipeline ADC is designed and implemented based on SMIC 0.13?m process,and a four-channel 12-bit 400MS/s time interleaved ADC circuit platform is set up by using it as a sub-channel ADC.The output of the platform is used as excitation signal and inputs to the calibration algorithm in FPGA.For the calibration scheme based on statistics method,with offset mismatch os=[0 0.05-0.050.1].gain mismatch Ag=[0 0.053-0.971 0.042]and timing mismatch At=[0 1%2%-1%]Ts,sampling frequency fs=400 MHz,a differential swing 0.9Vpp 164.6 MHz input signal,after calibration,the signal to noise and distortion rate(SNDR)and spurious free dynamic range(SFDR)dynamic performances of the TIADC rise 48 dB and 60.2 dB,achieve to 71.2 dB and 84.6 dB respectively,the Effective Number of Bits(ENOB)is improved to 11.5bits.For the calibration scheme based on signal modulation,the offset mismatch error is not considered,verification results show that,with the same gain and timing skew mismatches errors and simulation conditions,before calibration,spurious free dynamic range and signal to noise are only 30.9 dB and 53.8 dB respectively,after calibration,SNDR and SFDR rise 40.5 dB and 54.7 dB,achieve to 71.4 dB and 88.5 dB respectively,the Effective Number of Bits rises to 11.52 bits.Finally,based on the SMIC 0.13?m technology,an cascoded calibration algorithm based LMS iterative adaptive calibration algorithm with its own channel is designed by ASIC,and the post-simulation results showed that the proposed digital calibration technique can effectively suppress the spurious effects caused by the interlaced ADC channel mismatch error,and greatly improved the Dynamic performance of TIADC.