A Research On Digital Calibration Techniques For The Time-Interleaved ADCs

Rapid developments of information technology and integrated systems have strong growing demand for high performance ADCs. However, with the development of CMOS process, the design of high performance ADCs are challenged by more obvious nonideal factors brought about by scaling down of technology, low supply voltage, low transistor intrinsic gain under deep submicron and nanometer process. The performance of single channel ADC approaches to the technology limitations on speed and accuracy in the present conditions. Multi-channel Time-Interleaved ADC (TIADC) is a necessary and an effective way of breaking through technology restrictions and speeding up high resolution analog-to-digital conversion. Offset mismatch, gain mismatch, and timing skew mismatch among channels, however, severely restrict the performance of TIADC. With large scale integrated circuits’ advantages on process, intergration, cost and power, using digital calibration for breaking through the performance bottleneck of analog circuits will be the general trend of high speed high resolution TIADC design in future.This thesis researches digitally assisted design technique for high performance TIADC. Exploring universal design principle and design flew of the digital assisted analog integrated circuits. Depending on the completeness of digital signal processing knowledge,achieving digital calibration by using digital post processing technique to inhibit the detrimental effect on dynamic performance of the TIADC resulted from the mismatches among channels. Designing system-level, behavior-level and circuit-level verification platform for completed design and verificationFirstly, A novel mutual-prime-channel-group TIADC based on split-ADC and its general architecture are presented. The sources of channel mismatch errors and the error effects are studied systematically, and a channel model with mismatch errors is given. System architectures, basic theories, and algorithm implementation of TIADC with channel mismatches calibration are thorough discussed. On the basis of split-ADC calibration concept, basic principle of time-interleaved ADC using split design technique is researched in depth, sufficient conditions and design method of mutual-prime-channel-group TIADC based on split-ADC are presented.Secondly, all-digital channel mismatches calibration technique aiming at the mutual-prime-channel-group TIADC is presented. This technique can adaptively calibrate offset mismatch, gain mismatch and timing skew mismatch among channels simultaneously at background, eliminating performance limitations which are brought about by mismatches for TIADC. The calibration algorithm is based on least-mean-square iteration which has advantages of low computational complexity and easy in complementation. To guarantee effective calibration when input frequency of the TIADC is high, a cascaded compensation scheme for correction of high-order timing skew errors is employed and good calibrating performance is demonstrated with normalized input frequency near Nyquist frequency. In this thesis, a7-channel split-ADC based TIADC is taken as an example to prove the architecture of mutual-prime-channel-group TIADC and its mismatches digital background calibration. Moreover, the proposed architecture and the associated calibration technique can be expanded to channels of any number.Finally, a14-bit125MS/s pipelined ADC is designed, and using it as channel unit for developing a circuit platform of the proposed TIADC architecture, in combination with the implementation of the calibration algorithm by FPGA, verifications for the correctness and the practicability of the proposed TIADC architecture and calibration scheme are done. Verification results show that, with3%full scale range offset mismatch,2%gain mismatch and2%sampling period timing skew mismatch, spurious free dynamic range and signal to noise and distortion rate improve about50dBc, achieve92dBc and84dBc respectively, effective number of bits improves8bits, achieve13.7bits which approaches the single channel resolution of the TIADC. This reveals the proposed digital calibration technique does eliminate the nonideal effects brought about by channel mismatch and improves TIADC dynamic performance.