The Research On The Low Power Physical Design Of The SoC Chip

With the fast development of the technics of semiconductor, the scale of design and integration is becoming more and more higher, Integrated circuits has entered the SoC (system on chip) era. However, the power comsumption is the bottle-neck problem of the SoC design, and becomes the same important design target as the acreage and performance. So the low-power design has became one of the serious challenge of SoC design.The dissertion researches the methods of the low-power design of a SoC chip. The purpose of designing the chip is to gain the much lower power on condition that the performance of the chip is right. In order to reach the the require of low-power design, the dissertion reseaches the three aspects below, which are acreage optimization, clock gating insertion, clock network design.Firstly, focusing on Floorplan, the dissertation raises a reasonable method for the SoC chip with the multi-chip encapsulation structure, which contains the decision of the acreage and the floorplan of IO pad, IP core and standard cells. At the same time the dissertation raises a clock-network design method for the multi-metal-floor design. The method can connect the power sufficiently under the little routing resource and provide a sufficient routing resource for the next placing and routing. Secondly, we reasonablely use the clock-gating insertion method for the design which is putting the clock gating between the modules and standard cells of a module to realize dynamic power management. It makes sure the require of the low power. Finally, analysing the existed structure of the clock network, the dissertation provides two schemes for this design. One is a advanced design method named MLTAS(mesh+local tree auto synthesis) which bases on the MLT(mesh+local tree) structure and can effectively reduce the numbers of the buffer and the clock skew, while the other is LPCTS(low power clock tree synthesis) that can reduce the design period. Comparing the two methods, we choose the LPCTS as the more suitable clock-network design method for the low power design at last.The research SoC chip of the dissertion is designed with the Encounter tool of Cadence, which employs the 0.18um process with the six-floors metal and bases the standard-cells'design mode. Then the dissertion does the emulational analysis for the IR Drop and power. So the power integrality is validated and the require of low-power design is satisfied. Lastly, it contrastively analyses the emulational result and the actual testing result of the SoC chip, which validates the correctness of the chip design.