Design Of Radiation Hardened SRAM Using Commercial Process

With the development of space technology, more and more integrated circuit has to work in the radiation environment. As one of the prominent members of semiconductor memory, SRAM(Static Random Access Memory) is highly sensitive to the SEE(Single Event Effect). And SEE can range from data errors of memory to permanently spoil the device. Thus, researching SEE and the harden method of SRAM is quite essential.This paper adopts commercial silicon technology to design an Radiation Hardened SRAM with 1024x16 bit, and has a simulation verification of layout to match the design requires. Compare to the commercial SRAM, the performance of the resist SEU(Single Event Upset)and SEL(Single Event Latch-up)has been proved significantly.The mainly work of this paper:1) Briefly state the mechanism of SEU and SEL. Drawing a conclusion from analyzing the sensitive reason of common SRAM for the SEE, and the memory unit is very sensitive to SEU.2) Summarizing three types of hardening: technology level, design level, system level. Assessing the resist SEU in memory unit which uses HIT, DICE, QUATRO circuits harden structure. Comparing the structure of DICE and QUATRO circuit. As a result, the amount of sensitive nodes from DICE structure was two pairs more than QUATRO. Meanwhile, the harden effect was likewise better than DICE.3) Circuit Pattern: in order to harden SEU and debase the sensitive nodes, I use QUATRO memory cell to design the redundant storage nodes.4) Layout Pattern: It effectively reduces the SEU by charge sharing after modifying the memory cell of layout. Harden SEL by increasing the contraction of well and substrate to reduce the shunt resistance, and extent the space of source area between NMOS and PMOS transistor.