Design And Implementation Of SEU Tolerant Robust Cell And ECC Encoding On SRAM

The implementation of semiconductor circuits and systems in nano-technology makes it widely used and achieve larger scale, higher speed and smaller area. The undesirable result of this scaling is that it makes integrated circuits susceptible to soft errors normally caused by radiation. These events of radiation strike resulting into information loss or functional failure in memories referred to as Single Event Upsets(SEU). With the decrease of feature size, Multiple Bit Upsets(MBU) in memories becoming more widespread and complex, which is noteworthy in the current mainstream technology. As the most sensitive part of the chip to instantaneous interference, Static Random Access Memories(SRAM) in the field of nuclear technology, space applications and crucial civilian have a strong demand for fault tolerance.This thesis focuses on the mechanism of single event upsets and the design of radiation hardened in SRAM. The simulation and modeling are realized by Technology Computer Aided Design(TCAD) software. The sensitivity to SEU of transistors in SRAM are verified using Sentaurus software by circuit/device mix-mode simulation. In the analysis of the influence of series factors, different Linear Energy Transfer values, incident positions and angles of single particles are both taken into consideration to verify the effect on SRAMs.Aiming at the frequently occurring SEU in SRAM, this thesis analyses the charge collection in the sensitive region and radiation hardened by design(RHBD) technology, then proposes three SEU tolerant robust storage cell, which are cross-connected-structure, read/write-split-structure and isolated-structure. In the radiation hardened design, the reinforcement storage units could reduce the cost because of common CMOS process. By circuit/device mix-mode simulation, the resistances to SEU caused by single particle radiation of three structures are obtained. These proposed SEU tolerant robust cells are able to recover the SEU at 173.8Me V-cm2/mg, 164.2Me V-cm2/mg and 135.2Me V-cm2/mg on the single node, respectively. By adding a single particle radiation to a plurality of sensitive nodes in each SEU tolerant storage cell, the ability to resist multiple sensitive nodes upset in these structures is evaluated under different conditions. The isolated-structure can recover the SEU at 77.3MeV-cm2/mg on multiple sensitive nodes.It is proved that these three SEU tolerant robust storage cells achieve the function of SEU tolerance very well.In the view of MBU effect in SRAM, this paper studies the RS code based on Error Correction Code(ECC) and designs the corresponding RS-based error correction circuit to reduce the error rate of MBU on SRAM. The proposed error correction circuit is implemented in Verilog HDL and the error correction capability of the proposed circuit is simulated in Modelsim by the method of error injection. As the results reveal, the RS code, which has high error correcting capability, can correct 8-bit errors in two consecutive symbols and errors occuring discontinuously in information bits. Compared with other error correction codes, RS codes have advantages in correcting more multiple bit upsets.