Design Of Hardened SRAM Cell And Memory

With the development of integrated circuit and aerospace industry,System on Chip(So C)are more and more used in the radiation environment.Memory is an important part of So C,the memory radiation hardening is a key research area of today's memory.In this paper,a SRAM memory for anti radiation So C is designed by using SMIC0.18 ?m process.In this paper,the Single Event Upsets effect,Single Event Latchup effect and Total Ionizing Dose effect,as well as the common hardened methods are analyzed,and the hardened methods used in the design are determined according to the three radiation effects.Subsequently,the architecture design and timing design of 8Kb memory are carried out according to the design requirements.In order to strengthen the circuit level of memory cell for Single Event Upsets,a memory array is designed by using 12-tube DICE circuit.Then,the peripheral circuit of memory is designed and simulated,including row and column decoding circuit,data input /output circuit,sensitive amplifier and clock circuit.The structure,function and performance of latch type sense amplifier are analyzed emphatically.Completed the entire memory design and simulation,the design of the SRAM memory frequency can reach 100 MHz.The access time is about 0.926 ns and the power consumption is 3.88 m W.Finally,the layout design is carried out,and in the layout,the Single Event Latchup and the Total Ionizing Dos are reinforced by power contact and substrate contact,and the memory layout size is 603900.3432?m2.The parasitic parameters are extracted and simulated,the simulation results show that the function of the memory is correct.The access time is 1.21 ns,and the power consumption is 5.136 m W,which is not much different from the previous simulation results.