Research And Implementation Of PIPE Interface Adapter Based On FPGA

With the rapid development of integrated circuit design and manufacturing technology,chip integration improves continuously. multi-core So C system level chip has replaced traditional single-core CPU. The more magnificent design scale of modern So C system is, the more important So C chip verification is. How to carry out the design verification quickly and efficiently has been the key problem of chip design. In the verification of Large scale So C, hardware simulation accelerators that is of rapid speed, high capacity and high performance are used.When using hardware simulators for So C chip simulation, the highest speed of simulation is less than 6 MHz.When directly simulate the PCIe and SATA high-speed universal serial bus,because of the low speed,it’s not able to connect the real device under such simulation environment.This article has carried on the problem systematically and puts forward a design method of PIPE interface adapter on the basis of the principle of asynchronous message transmission and PIPE agreement. Then a PIPE interface adapter is implemented to provide solutions on connecting real PCIe equipment in the hardware simulator environment. In this paper, the main work and innovation points are explained as follows:1. To research the PCIe protocol based on the hierarchical structure of the agreement of PCIe and the practice that mainstream PCIe controller separate MAC layer and physical layer. A physical simulation model is determined to implement hardware simulator connection between the devices and real methods.2. To research the physical layer PIPE interface specification and to analyze the sequence of PIPE interface message. According to the message characteristics of the PIPE interface and the asynchronous transmission method, a cross asynchronous clock PIPE adapter design method was put forward.It has solved the periodic message such as credit synchronization and transmission method.3. According to the aforementioned methods, A PIPE interface adapter for PCIe agreement is implemented and the problems of connections are solved between slow simulator platform(below 10 MHz) and the real PCIe equipment.4. Based on the KC705 development board, the PIPE interface adapter is simulated and the PCIe interface to DDR3 SDRAM controller data transmission channel is established to test the PIPE interface adapter through a large amount of data transmission.