Design And Implementation Of A Hardware Emulator For PCIe Bridge

In recent years, system on a chip(SoC) has obtained the swift and violent development.Compared with the traditional chips,system on a chip not only contains a large number of hardware module,but also is is equipped with a large number of software,such as operating systems, communication protocols, as well as a variety of related applications, and so on.The design of the scale and complexity is much higher than the traditional chips.The simlation of chips with this SoC is also becoming more and more important.In large scale of system-on-a-chip(SoC)verification, hardware simulator this rapid performance, high capacity, high simulation tools are adopted gradually.Hardware simulator for large-scale SoC chip during the simulation, the simulation speed is generally not more than a few MHz which makes it no connect with the real equipment when simulating for the high-speed serials such as not drop PCIe frequency, SATA,and so on in simulation environment.In view of the problems described above,this paper proposes a design method of PCIe bridge,which provides a solution for the connection between the real PCIe equipment and hardware simulation environment, and its main contents are as follows.1, in this paper, on the basis of PIPE agreement, designed a model on the basis of the principle of the asynchronous transmission of a message PCIe bridge, including the PCIe bridge link recognition module, message parsing module, message scrambling module, message one module, flow control module, and a message across the clock domain transformation mechanism.Implements the slow the speed of the hardware simulator with fast PCIe equipment matching, solves the hardware simulator does not support analog hybrid simulation.2, for PCIe link more closely to observe and control, makes debugging difficult.This paper designed the link listening device, which can realize the PCIe master-slave real-time monitoring of the message transfer status of the equipment, convenient for the user to observe and revision link transfer status, system commissioning and validation.3, in order to meet the PCIe bridge in different hardware from the use of the simulator, this paper adopts general PIPE protocol design, the design of the PCIe bridge can support configuration x1, x4, by 8, x16 link of transmission, and may be similar to the PCIe interface adapter to solve the problem of the PCIe bridge compatibility.4. Insert the PCIe bridge actual PCIe IP, set up the system level verification environment.Simulation environment including CPU_SIM module, insert IP, PCIe_Device_Sim PCIe bridge module, used to simulate the CPU and PCIe equipment communication environment, verify the correctness of the PCIe bridge.In PCIe_Device_Sim module design, the DMA controller by the working frequency of 500 MHZ PCIe equipment itself and CPU_SIM module under 1 MHZ, 2 MHZ and 5 MHZ compared the status of the link, to verify the correctness of the PCIe bridge function, based on the comprehensive analysis and PCIe bridge test for PCIe link bandwidth and low frequency condition, to analyze the performance of the PCIe bridge and argument.V...