Design And Verification Of Commucation SoC Chip PCIe 2.0 Interface

PCIe is a high performance and error monitoring mechanism and reporting mechanism of the third generation interconnection of I/O bus,if PCIe directly connected to system bus,not only will take a lot of resources,but also affect work efficiency seriously,therefore highspeed PCIe interface circuit needs to be specially designed to satisfy the need of PCIe and system bus.The AHB bus protocol that based on ARM is designed for special high speed PCIe 2.0 interface circuit,and APB interface is used to configure PCIe.In this paper,the design of high speed interface can greatly reduce the pressure of PCIe bus system and improve transmission efficiency.The main work is as follows: firstly,this paper has completed the design of S2 C AHB and C2 S AHB interface,through the analysis of AHB protocol,the function of single beat transmission,four beat incremental transmission,eight beat incremental transmission,sixteen beat incremental transmission and 7 bytes of data transmission are achieved.In addition,the design of APB interface has completed,through PCIe protocol,register segment is allocated,256 bits descriptor has been designed,and the meaning of all segment of descriptor are described.Then PCIe verification platform is built,and the function of interface circuit that is designed is verified.According to interface function requirements,specific verification items is constructed,including: read and write verification of APB interface;verification of PCIe traditional interrupt verification and MSI interrupt;verification of single beat transmission,four beat incremental transmission,eight beat incremental transmission,sixteen beat incremental transmission and 7 bytes of data transmission which belongs to S2 C AHB interface and C2 S AHB interface;the verification of target read function and target write function.Finally,interface performance is calculated,through the calculation of waveform performance,the performance of S2 C AHB interface is 330MB/s,and the performance of C2 S AHB interface is 500MB/s,which meet the performance requirements.This paper has completed design and verification of PCIe special interface circuit,results show that design of interface function and performance meet the specification requirements and achieve expected goal.