Design And Implementation Of PCI Express System In X-MDSP Chip

Digital Signal Processors(DSPs) has been widely used as one of the key components of modern electronic devices in various applications like military, aerospace, supercomputer and communication. Meanwhile, with the development of integrated circuit technology and the advance in microprocessor architecture, computation performance of DSPs has substantially increased. But the improvement of bandwidth of high-speed interconnection infrastructure for off-chip communication is relatively slow, which gradually becomes a bottleneck that restricts the overall performance of DSPs. PCI Express is the new generation of high-speed interconnection bus protocol that originates from the requirement on bandwidth for off-chip communication in such background. PCI Express has been widely adopted in the industrial field due to its high data rate, low propagation delay, low power consumption and simplified signal interface.X-MDSP is a high-performance and high-bandwidth multi-core DSP independently developed by Computer School of my university. Its high and parallel computation capacity require s high data throughput of the entire system. PCI Express is adopted in X-MDSP as the off-chip communication infrastructure to achieve high speed data transfer between the chip and external devices, providing required off-chip bandwidth. The main contributions of this paper are as following:(1)We first systematically analyzed the off-chip interconnection requirements of DSPs and the protocol of PCI Express. The analysis results serve as a guideline to build the overall structure of PCI Express system.(2)The protocol bridge is implemented between the AXI interface of the PCI Express controller and the internal interconnection network. This bridge mainly realizes the protocol and clock domain conversion between AXI /configuration interface of PCI Express controller and I/O interface in chip interconnection network.(3)This paper finished the function design and parameter configuration of IP core, as well as the connection among the bridge, PCI Express controller, and the PHY. The main contents of function design include: clock and reset network for PCI Express system, initialization for PCI Express link, register-based data transfer path, DMA-based data transfer path, INTx and MSI interrupt mechanism.(4)A verification environment is built to verify the function of the PCI Express system in detail. We then evaluated the transfer bandwidth of PCI Express link, as well as the timing and resources of the whole PCI Express system. Based on these results, we further analyzed the transfer performance of bridge in terms of both transfer bandwidth and transfer delay.Verification and performance analysis results show that, with reasonable hardware cost, the implemented PCI Express system can work robustly, achie ve required timing closure, and meet the performance requirement.