Key Techniques Of Network-on-Chip Design For Multi-Core System-on-Chip

With the development of technology and the increase of application requirements, the complexity and capacity of SoCs will continue growing in the future. A single chip in the next decade may contain hundreds of IP cores, including RISC cores, DSP cores and storage elements. In the multi-core SoC designs at such scale, one key issue is how the various IP cores communicate with each other. Therefore, on-chip communication systems with high performance, low power and good scalability for future multi-core SoCs have become a hot research field in recent years.Traditional on-chip communication structures, such as buses, can't satisfy the requirements of current multi-core SoC designs. Network-on-Chip (NoC), a communication-centric technique, provides a new solution for communication problem of multi-core SoCs. This dissertation focuses on the design and optimization of NoC in multi-core SoCs. According to the communication features of one target system, multi-core DSP, the dissertation analyses the key techniques of NoC design, and makes a study of the design methods on reducing power dissipation and area overhead on the premise of satisfying the needs of high-performance communications. The main works and contributions of the dissertation are as follows:1) In the physical layer of the NoC communication stack, a hybrid insertion strategy based on full-swing repeaters and low-swing transceivers, HI (Hybrid Insertion) strategy, is proposed for global interconnect implementation. The HI strategy can be used to balance interconnect delay and power dissipation well, which is the main shortcomings of current repeater insertion schemes and low-swing transmission schemes. The optimal parameters, including the number and the insertion interval of repeaters and low-swing transceivers required for the HI strategy, are derived and proved in the dissertation. It is shown that the HI strategy can reduce interconnect delay, power dissipation and area cost effectively.2) For lack of general high-level estimation models of low-swing interconnects, a three-dimension lookup table based estimation model, LSIEM (Low Swing Interconnect Estimation Models), is presented on the base of the HI strategy. Firstly, the overall framework of LSIEM model is given in the dissertation, and corresponding model can be used to estimate the delay, power and area cost of long wires rapidly during early design stages. Moreover, an OWS-HI (Optimal Wire Sizing for Hybrid Insertion) scheme is proposed by using the LSIEM model. The scheme can be used to optimize the wire size of the HI interconnects. Experiment results show that, compared with HSPICE simulation, the LSIEM model (delay estimation model and power estimation model) has the accuracy of more than 90% and increases computation speed 95 times.3) Also in the physical layer of the NoC communication stack, a new asynchronous FIFO structure, WG-FIFO (Weighted-Gray code FIFO), is proposed for global synchronization. The WG-FIFO encodes write/read pointer with a new Weighted-Gray code, and controls write/read operations with real-time global states detectors. Therefore, the proposed FIFO can overcome some shortcomings of existing asynchronous FIFO designs, such as conservativeness, inefficiency and waste of space. In the dissertation, the overall structure of the WG-FIFO is described in detail, and the validity of pointer coding mode and state detection mechanism is analyzed in depth. Simulation results show that all of throughput, area cost, and write/read operation efficiency for the proposed FIFO can be effectively improved in the depth range of 4～16, compared with other available FIFO designs.4) In the network layer and network adaptor layer of the NoC communication stack, a clustered hierarchical NoC design, LSGT-NoC (Locally Star Globally Torus Network-on-Chip), is proposed according to the communication features of the target multi-core DSP. The LSGT-NoC design can make a good balance between performance and power dissipation. In the dissertation, the hierarchical LSGT (Locally Star Globally Torus) topology and the transport protocol supporting multicast transmission are introduced. And the essential components of NoC, such as switch, network interface and global link, are implemented. Furthermore, the low-power optimization methods of crossbar and global link are explored especially. Simulation results show that, LSGT-NoC has the advantages of small hop numbers, high bandwidth, low power, and good scalability.The research in the dissertation provides a feasible solution for the communication problem in multi-core SoCs, and the results can be used to further improve practical parallelism and performance of multi-core SoCs.