The Desigen And Implementation Of The Inter-chip Asynchronous Bridge In The Muti-Core SoC Based On The PCI Express

Along with the increase of application, the single core DSP can not be meet by the operation requests of specific application such as 3G mobile communication, the digital consume electronic product and the intelligent control device and so on. With the development of technological technology, multi-core SoC has the application demand and the supporting of related software and hardware , therefore multi-core SoC has gradually become researchful focus and been promoted and applied widely.The XX-XDSP is a heterogeneous muti-Core SoC baseing on the XX-DSP. Currently, in order to meeting the need of the high performance digital signal processor and the high speed transmission of data among several SoCs, The XX-XDSP adopted a new interconnection mechanism. There are inter-chip interconnection Qlink module, the inter-module interconnection Crossbar, the asynchronous Bridge (Qlink_PCI Express Bridge), and the PCI Express module which realized communications between chips. In our multi-core SoC system, the Asynchronous Bridge realized the conversion bewteen the Qlink protocol and the PCI Express protocol;The PCI Express was a interconnected I/O port between chips. The article designed the Qlink-PCI Express Bridge basing on the interconnection mechanism.The main work and contribution is as follows:First, we analysed the PCI Express architecture, and understand its structure and transmission properties. In order to saving the area of the chip, we cut down the config space and many channels of the PCI Express in work.Second, we successful designed the asynchronous bridge., realized the inter-chip interconnection function , and the asynchronous bridge. could correct complete the conversion of the Qlink descriptor to the PCI Express descriptor,.Finally, being lacking of the the physical layer of the PCI Express ,we successful constructed the environment of the simulation by directly connecting the PIPE layer of the PCI Express, and designed the 4 SoCs' environment of the simulation, all-around simulated and verified the asynchronous bridge module. The result indicated that the function of the asynchronous bridge is correct in the inter-chip interconnection structure, and the average efficiency of the inter-chip interconnection structure can reach more than 1.55G/s. After being synthesized in the standard of 0.13μm,the area of the asynchronous bridge module and the inter-chip interconnection module were 0.12μm~2 and 0.65μm~2, accorded with the requirement of the chip.