The Analysis And Simulation Of FPGA Timing Convergence

The field programmable gate array has been developing rapidly in 30 years. Due to some advantages like the flexibility, the shorter development cycles and the Lower development costs, FPGA is used widely in various fields. With the FPGA design becoming larger scale and higher performance, its timing convergence has increasingly become a big issue in the FPGA design. This paper discusses the FPGA timing convergence analysis and simulation.This paper introduces the internal structure and the timing sources of FPGA. Then, a simple model of sequence circuit is built and analyzed, and it is used in the FPGA timing analysis below. In this paper, various sequential paths in FPGA are analyzed in depth, and we mainly analyzes three aspects including input/output logic, synchronous sequential logic and asynchronous sequential logic. and timing design in FPGA is discussed and researched by introducing some cases of design.In this paper, the main research object is the FPGA design of DDR2 SDRAM interface. DDR2 SDRAM is a kind of high speed memory, its data rate is twice of its clock frequency, and data transmission between different clock domains is a huge challenge for the timing performance of the FPGA design. Therefore the datapath between FPGA and DDR2 SDRAM is the critical timing path in this design. This paper mainly researches the structure of the datapath and the synchronization of the data transmission by timing analysis, and timing simulation of this design is carried out. Finally, we discuss the timing performance of DDR2 SDRAM interface by referencing the timing constraint and the report of static timing analysis.