The Fpga Static Timing Analysis And Design

STA (Static Timing Analysis) is an important module in the FPGA software system. It is used to calculate the delay of the design, the speed of the circuit, and verify whether the circuit meets the timing constrains. Static timing analysis technology has great advantages in functionality and performance, and now basically almost all digital circuit design needs to pass the STA analysis. There are many differences between the STA of FPGA and the STA of ASIC. FPGA has fewer basic components but more complex interconnect structure, while interconnects of ASIC circuits are simple. And what’s more, the delay of the interconnect resources are different for different FPGA chips, so you cannot get an accurate results with other company’s STA tool. It is very important to get accurate STA software for us.We spend long time to investigate interconnect timing library for FPGA and do a statistical analysis on interconnect timing library. The thesis put forward the logarithm inputs method and cumulative frequency inputs method creatively to enhance the simulation accuracy of the STA. The new method the thesis present can solve the problem of the traditional timing library, in which there are too many negative values and the library has low utilization of the data.And in the thesis we put forward the software regression test platform, with which we can easily test the different cases and different version’s software. The thesis also presents the soft-hardware test platform for the STA of FPGA software system. The tests show that the STA software can work properly. The interconnect timing library based on cumulative frequency method can greatly improve the simulation accuracy of the STA. The results show that the Logarithm simulation input method and cumulative frequency inputs method can get the PR ration to89%from38.56%while can rich8.23%error while the old method can only reach13.58%.