Research And Implementation Of Static Timing Analysis

Static Timing Analysis, STA, is a kind of timing performance analysis techniques which input stimulus is not necessary. In the field programmable gate array (FPGA) CAD software system, it is an significant component, whose role is to investigate the circuit delay of FPGA users’design, the criterion of circuit speed, the worst-case timing analysis, and all these statistics verify circuit performance at this time to meet the timing requirements of the user, so that ensure the circuit can operate normally in any case. Static timing analysis technology has great advantages at functionality and performance. Because of needless any excitation signal, high speed and fully verified of circuit design can be achieved, almost all digital integrated circuit design needs through static timing analysis and simulation. However, static timing analysis in FPGA software system is different with those in ASIC.In the FPGA chip, the basic logic elements are relatively fewer, and the interconnection of resources relative to the ASIC is more complex, which representing the higher proportion of chip resources. So compare with the ASIC, FPGA chip timing modeling interconnect resources is even more important. In addition, for different FPGA chips, interconnect resource properties are not the same, resulting in the delay of information interconnect resources are completely different, so in addition to design appropriate STA software, but also the need of building different FPGA chips accurate interconnect timing library resources is urgent. To solve the above problems, this paper pays attention to the following tasks:This article investigates the structure of the FPGA chip architecture and interconnect resources, establishes tree data structure according to circuit interconnect network, and calculates the delay circuit interconnect. What’s more, circuit timing information can be obtained by using critical path.In this paper, HSpice simulation is used and building a library of resources timing for FPGA programmable switch resources. What’s more important, timing information of programmable switches at different load capacitance and those under different input signal transition are stored in the form of two-dimensional look-up table in the interconnect timing library resources for STA runtime module.In this paper, test scripts written in Perl, achieving an efficient automate way to verify static timing analyze modules.