Universal Timing Optimization Fpga Packing Algorithm

A complete FPGA design flow includes FPGA hardware architecture design and the corresponding software system design. Software design should match hardware design. If the architecture of FPGA varies, it's likely that for each newly produced FPGA, its corresponding software should be redesigned, which makes both research and production more inconvenient. That's why it's really necessary to develop a general software system which applies in various situations. Mapping is an important part in FPGA software design flow, while packing is a sub-operation of mapping, and packing is equal to mapping in many cases. For the procedure of Packing is closely related with the architecture of FPGA, the universality of Packing algorithm is the key problem to solve. Domestic and foreign researches on universal Packing algorithm are mainly based on the ideology of pattern matching in math, one example is PLBMAP, which has breakthrough on both area saving and run time. Nowadays, timing problem becomes the top bottleneck instead of area saving in circuit design. Unfortunately, PLBMAP has unsatisfactory performance.A new universal packing algorithm TDU-Pack will be introduced in this thesis based on the further research on this ground. This algorithm analyses the common part of modern FPGA logic structure, models for different kinds of FPGA structures, which can be applied in various kinds of FPGA with good universality. Focused on timing optimization, TDU-Pack get the timing information of user circuit by the way of simple timing analysis, and counts the timing criticality to guide the procedure of packing. Experiments have proved that TDU-Pack has better performance than PLBMAP, and can be applied in academic FPGA structure and various commercial FPGA structures. On the academic platform TDU-Pack shows the performance that can be compared with academic T-VPack, while it also shows the similar performance with commercial software on the commercial ones. TDU-Pack is the further achievement on universal FPGA packing algorithm.