Design Of Self-adaptive Method For SDRAM Timing Diversity Based On FPGA

Since 2010 the competition among memory suppliers kept getting intensive,especially for SDRAM product vendors continuously update the production process every 1 or 1.5 years in order to keep their competitiveness.However,even the process and production control capability kept upgrading the consistency of DDR3 timing features couldn't be guaranteed.Therefore,no matter applications began to adopt new process SDRAM of the same vendor or any SDRAMs of a new vendor the matching condition between the timing configuration of the applications and the timing feature of the specific SDRAM must be carefully inspected.There are two methods mainly used while settling timing mismatching issue including timing calibration and timing adjustment through hardware setting.However,those two methods are not flexible ?but complicated and time consuming;for cost sensitive and time sensitive projects the defects would be fatal enough to block the progress of mass production.It is highly meaningful to find an efficient way for applications to easily accommodate SDRAM components that had diversified timing features backup by effective verification method.Based on SDRAM calibration methods this thesis sets DDR3 as research subject and targets on how to make applications efficiently support DDR3 components that had diversified timing features.In the thesis the operation of DDR3(Double Data Rate 3rd Generation SDRAM)had been carefully studied,based on which the most popular timing calibration methods being universally used had been analyzed.The calibration methods designed to be effective for DDR3 components that had similar timing features rather than flexibly for DDR3 components had diversified timing features.In order to solve the problem based on the operation specification of DDR3 the fundamental reason of timing violation caused by diversified timing features of DDR3 components had been identified,then a self-adaptive method had been proposed to deal with the timing feature differences among DDR3 components.The method was about using software method to make adjustment to the timing sequence between key signals,then using different timing configuration setting to self-adaptive match DDR3 components that had diversified timing features.When applying the self-adaptive method to a specific application and designing verification methods,Xilinx software platform Vivado and Kintex7 evaluation board were used.In the verification test DRAM components that had highly diversified timing features were used and validate the effectiveness and efficiency of the self-adaptive method proposed in the thesis.