The Research Of High Performance Digital Pulse Width Modulator

With the development of application systems such as wireless sensor networks(WSNs),automatic control systems,and implantable power systems,the performance requirements for their power management systems are also increasing.Traditionally,the control technique of the power management system includes analog circuit control and digital control.However,due to the complexity of system functions,digital control technology has gradually become the common control technology for complex systems owing to its advantages such as good applicability to complex algorithms,programmability and portability.One of the most crucial part in a digital control loop is Digital Pulse Width Modulator(DPWM).In recent years,most research about DPWM has focused on improving linearity and time resolution.However,with the increasing of system resolution and the complexity of control algorithm,the logic and interconnect delays in the critical path of DPWM will interfere with the DPWM timing,resulting the non-linearity of output pulse.In the existing research,few works has been done to optimize the critical path.When the DPWM is applied to a high resolution digital control system,the critical path delay may cause system breakdown.In view of the above problems,this thesis propose a segment delay DPWM.The DPWM structure includes three delay units with different precision,including counter,phase shifting unit,and carry chain.This structure divides the high resolution data stream into three parts for different precision delay units,thereby improving DPWM resolution.In order to eliminate timing problem introduced with the increasing of the resolution,this thesis designs a new synchronous phase shift circuit and optimizes its timing to eliminating the nonlinear phenomenon.At the same time,in order to improve the time resolution and linearity,the carry chain is optimized to guarantee the overall performance of DPWM.Finally,a pulse width compensation technology is applied to offset the critical path delay,which ensures the accuracy of output pulse.The DPWM proposed in this thesis is validated in the Cyclone IV series FPGA.it achieves a high linearity where R~2 maintains more than 0.9994 for a 14-bit,1.469MHz switching frequency DPWM.The output duty cycle covers a wide range from 0.9429%to 99.2%and the time resolution is about 41.3ps.