The Full-custom Design Of FPGA Programmable Logic Blocks Based On 65nm Technics

Field-programmable gate array with high stability, high flexibility, fast, high integration and other characteristics, has applications in many fields. Programmable logic block(CLB) on FPGA logic design is an important module, generally contains the lookup table and configured register, as well as fast carry chain, its design architecture can directly affect the entire FPGA design features for performance.To ensure the CLB has optimized system performance, minimal chip area, the largest system integration, This thesis uses a top-down full-custom design approach.First performed architecture design, and its reference to the functional and structural properties of CLB, as well as traditional design methods of CLB. Logic module consists of basic logic unit, and make improvements based on deep sub-micron process, in order to achieve the more optimized performance. Using simulation to optimize the experimental method to determine the overall architecture of the CLB.Then the module circuit design.Considering the basic function of the functional modules, frequency of use, configurability, flexibility and other characteristics, to design a lookup table circuit and configurable register circuit, fast carry chain circuit,a shift register chain circuit, distributed register circuit. During the simulation of programmable logic blocks, in order to ensure complete coverage of the function,design a complete simulation program, according to the authentication scheme for circuit simulation verification.The CLB uses 65-nanometer crafts, its lookup table has the six-input and each block contains eight basic internal logic unit. The CLB’s look-up table has wider logic functions, as well as small configurable memory logic levels. Compared with the130-nm four-input CLB, the desired design’s area saving 33%, 21% faster.