Deep Submicron Ic Feature Size Reduction Of Research, Development And Application

With the rapid development of integrated circuits design and manufacturing, the layout density gets higher and higher. Process shrink becomes an important topic for chip designers and manufacturers. In recent years, the device gate length has been reduced from a few microns to 65 nm and even smaller. This thesis focuses on the study of process shrink from 0.18μm to 0.144μm, the product design scaling is 80%.While the 0.144μm product keeps the same function perfomance as the 0.18μm product, the benefit of the shrinked process is its low cost for each chip and short developlopment cycle, therefore it can effectively and efficiently enhance the competitiveness of the product.However, the process shrink faces a lot of challenges from process, device matching and metal interconnect. The study on these points is focused through the whole project developing period. How to reach the shrink target was studied by theoretical analysis and lots of experiments. This thesis investigated major issues and presented the solutions that related to process shrink.In order to match the performance of device parameters, we adjusted process conditions including LDD plant, S/D implant, VT implant and poly length to meet the target. We also optimized process conditions to match interconnection performance. A lot of problems were found in process developing, but all of them are solved at last through process optimization. The process shrink targets were realized as follows(1) The product function of new process fully matched the requirement, the yield of the shrinked process was comparable with that before, and each wafer got more pass dies.(2) Inline and electric parameters were stable for mass production.(3) All reliability items including WLR (HCI、VTS、EM) and PLR (ESD and HTOL) passed.At last the shrinked process substituted 0.18μm process on the market with lower cost and equivalent product function.