| Due to the VLSI technology rapid progressing and the feature size continued shrinking, the density and operation frequency of IC have been increased greatly. In the stage of very deep submicron technology, the delay caused by interconnect in physical design has exceeded the gate delay, interconnect networks has become the dominant factor in determining circuit performance and reliability. The distribution of clock signals is critical to both the operation and performance of synchronous digital systems, therefore, the research on the design, routing and optimization algorithm for clock distribution network is more and more important.After reviewing the achievement of interconnect network modeling, clock distribution network design, routing and optimization, a novel stable delay calculation model for interconnect tree and a novel algorithm for constructing clock distribution network by simultaneously routing and wire-sizing are proposed.The new interconnect delay model is based on the distributed RLC parameter model. The new model calculates the"equivalent ABCD matrix"of the interconnect tree for approximations of transfer functions of the interconnect tree, and then derives the closed-form solution for the 50% delay by means of second-order moment matching and curve fitting. Simulation results show that the new model is much faster than the traditional methods and has an error of within 15% compared to HSPICE, at the same time it is stable.Based on the new interconnect delay estimation models, elementary research is performed on how to embedding the new model into the nonlinear programming based wire sizing method.In the end, according the achieved clock routing algorithms and wire sizing algorithms, a algorithm for clock distribution network construction by simultaneously routing and wire-sizing is proposed. The new algorithm can reduce the path delay by about 50% compared to the result which perform the Greedy-DME clock routing algorithm. |
PDF Full Text Request