Million-gate Soc Chips In Deep Submicron Physical Design Method

Nowadays Integrated circuit (IC) technology has entered Deep-submicron (DSM) and ultra large scale integration (VLSI) era, system on chip (SOC) has become a hot topic in IC design field. With technology and performance move forward, all kinds of parasitic effect in chip could have a great impact on the physical design of SOC. If still using traditional phsical design flow to today's SoC, it might take much time or else fail to achieve design in actual chip. Confronting with lots of challenges, a new physical design methodology must be explored so that we can accelerate the design closure and get a qualified chip.The paper studied and clarified a new physical design methodology to ultra large scale SOC chip in DSM process.At the same time I finished a five millions gate count multi-media chip physical design by Encounter tools. The paper introduced each major steps of physical design which cover global floorplan, power design, macro and standard cells placement, clock tree sythesis, routing and timing optimization. There were clarified in detail to these theory and resolving ways of crosstalk noise,IR drop, electronic Migration and process antenna effect. By myself, I chose some fitful ways to decrease chip power consumption and took some specail considerring for timing analysis so that we can make sure timing closure in actual chip.Now the chip in paper had a small volume commercial application. So these physical design methodology in paper is valuable and you can adopt them to the other DSM VLSI projects.