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Study On The Modeling And Hot Carrier Induced Reliability Of Ultra-deep Submicrometer LDD MOSFETs

Posted on:2006-03-28Degree:DoctorType:Dissertation
Country:ChinaCandidate:C L YuFull Text:PDF
GTID:1118360152471408Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
Hot carrier effect has a significant impact on submicron and deep-submicron scaling down MOSFET. The lightly-doped-drain (LDD) is an efficient process to improve hot carrier immunity of MOSFET. However, the parasitic series resistance and parasitic capacitance caused by the lightly doped region in the source/drain can reduce the drain current drive and the high frequency performance. The features such as channel length modulation (CLM), drain-induced barrier lowering (DIBL), velocity saturation, etc, are of some difference from the features in conventional short channel devices, thus increasing the complexity of the MOSFET modeling.In this work, one emphasis is put on the nonlinear modeling of LDD MOSFET, wherein the drain current Ids is the key of the MOS equivalent circuit. A semi-empirical model of DC I-V characteristics for ultra-deep submicron LDD MOSFET is proposed by employing empirical hyperbolic tangent description and theory of carrier saturated-velocity under high electric field. The model deals with the I-V characteristics in either strong inversion or subthreshold region. Also the smooth transition between linear and saturation region is guaranteed by th(x) description, avoiding the discontinuity of drain conductance. The parasitic resistance due to the lightly doped region is treated as an external parameter. Because the substrate current in LDD MOSFET still demonstrates an unique characteristics different from the conventional MOSFET, particularly in the very short gate length devices, and it is very sensitive to the hot carrier degradation, a novel substrate current model which is different from that for conventional S/D device is proposed for submicron and deep-submicron lightly-doped-drain (LDD) n-MOSFET, with the emphasis on the description of an important parameter - characteristics length l, which takes into account the effects of channel length and bias. The maximum lateral electric field Em, the length of velocity saturation region ld which are very sensitive to drain current and substrate current are significantly affected by this parameter. The substrate current model can be easily embedded in the model to match the related device measurement and explore the hot carrier degradation of the deep submicron devices. The modeling of the device is based on the methodology for the physical model and the empirical model, thus decreasing the computation consumption, maintaining the accuracy, and clarifying the mechanism of devices. The comparison between simulations and measurements for submicron and deep submicron LDD MOSFETs shows an excellent agreements.Further more, the accuracy of some parameters, such as the threshold voltage,drain-source parasitic resistance, the effective channel length, and the effective mobility, etc., is of great importance in the device's model. So we propose a novel parameters extraction method suitable for short channel length LDD MOSFET's. By subsection of the total gate bias range, the linear regression yields the gate bias independent parameters Rds, △L and μeff in a very small gate bias range. The repeat extraction operations in different subsections obtain the accurately gate bias dependent parameters in the total bias range. The method avoids the gate bias range optimization, retains the accuracy and simplicity of the linear regression extraction. The parameters are extracted from the measurements of the different gate lengths LDD NMOSFETs fabricated on 0.18μm CMOS technology, and as validity, are implemented in the compact I-V model. The excellent agreements between simulations and measurements indicate the effectivity of this technique.Another emphasis is on the different degradation behavior of ultra-deep submicron LDD NMOSFET from the conventional devices. Under the different stress conditions , including channel hot-carrier (CHC) stress and drain avalanche hot-carrier (DAHC) stress, the output drain current, the threshold voltage, the transconductance, the substrate current, the lifetime, etc., show the self-limiting time-dependent HC degradation, suitable...
Keywords/Search Tags:hot carrier effect, LDD MOSFET, ultra-deep submicron, I-V model, substrate current, parameter extraction, stress, degradation
PDF Full Text Request
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