The Design And Realization Of Multiplier In 64-bit High Performance Embedded CPU

Multiplier is one of the key units of microprocessor. The main design principle for a multiplier is a tradeoff balance among structural, implementation complexity, speed and area. Multiplication is based on partial product additions. In general, there are two main steps to accomplish a multiplication: generation of the partial products and sumation of partial products. Booth arithmetic is discussed and some typical stuctures of the adder-array are analyzed and compared under this context. This thesis then proposes a novel architecture for 64-bit fixed-point tree multiplier, employing both carry-save adder and 4-2 compressor as its basic adder units under the frame work of a particular instruction set architecture. It offers the best efficiency in obtaining the sum of the partial products and improves the shortcomings of the original Wallace tree and other prior arts. At the end, this thesis reports the implementation of a 64-bit fixed-point pipe lined tree multiplier on both circuit and physical levels employing full custom design methodology.