Research On Semi-custom Design Method Of High-performance Parallel Multiplier

Multiplier is an important component of microprocessor, and directly affects the performance of the whole digital system. For this reason, study on design of high-performance multiplier is still concerned. On the other hand, the intense market competition has accelerated the product's entering the market, which requires the designer to shorten design time. In order to take into account the performance and design time, semi-custom design method based on standard cell library is used to implement multiplier. But the traditional semi-custom design method is restricted by standard cell's limited driving ability, and cannot realize the shortest path delay. Therefore, this paper presented design method of high-speed multiplier based on standard cell library extension. This method eliminates the disadvantages of traditional method.A 17 bit×17 bit signed digital multiplier was proposed in this paper. To improve the performance, the multiplier used modified Booth's recoding algorithm, a Wallace tree structure and design method based on standard cell library extension. It analyzed critical path using logical effort model, and by constructing cells with different driving capabilities, it implemented equal logical effort in each stage to achieve minimum path delay. Based on TSMC 90nm standard cell library, an extended cell library was generated, and the layouts of multiplier were implemented respectively. Compared to standard cell library, the multiplier implemented with extended cell library achieved a performance improvement of 10.87%. Experimental results show that the semi-custom design methodology based on standard cell library extension can improve circuit performance effectively, which is especially appropriate for designs with large loads.