The Design And Verification Of An 18-bit Configurable Multiplier Which Based On Modified Booth Algorithm

Multiplier is a very important arithmetic unit of high performance micro-controller and digital signal processor. Nowadays, high-performance multiplier is not only used in math arithmetic, but also playing a real important role in encryption, image and voice signal processing. The performance of multiplier will directly affect the speed of whole system, and even determines the frequency of the chip. Therefore, designing and optimizing the structure of the multiplier will greatly enhance the overall speed, area, power and other performance targets, which has been a research focus at home and abroad.This paper completed a design of an 18-bit configurable parallel multiplier IP in a FPGA chip, which based on a deep research of the theory of multiplier. This design has chosen the modified Booth algorithm which performs better and easier to achieve than other algorithm to finish the design, besides CPL circuits are used in this design. In this paper a flexible structure is used to achieve the modified Booth algorithm, reducing the complexity of circuit and layout. Further more, 3:2 compressor is used to compress the partial product of multiplier, and in this circuit a uniform solution to the modification of the subtraction of two's complement is provided. The difficulty of design is reduced by using the circuit. At last, the finally product output module select the carry-bypass adder structure. After completing the design of multiplier, a verification of the design is necessary, and the results of simulation indicated that the design had met the initial objectives.