Research And Design Of54b×54b Redundant Binary Multiplier

Multiplier is an indispensible arithmetic unit in digital signal processors, which is the key tocompleting high-performance real-time digital signal processing and image processing. To improvethe performance of processors, it is necessary to design a high-performance multiplier.Therefore,thestudy of high-performance multiplier has been a hot topic at home and abroad.The multiplier operations include three key modules:partial product generation, partial productaccumulation and final product generation. After in-depth analysis of algorithms and structure ofthese three modules, a54b×54b multiplier based on redundant binary(RB) is designed in this thesis.In the partial product generation stage, the Booth2algorithm is chosen after the comparison andanalysis of Booth algorithm and related algorithms, which reduces the number of partial products byhalf. Due to the carry-free feature and regular structure and interconnection of redundant binary adder,the partial products are accumulated in the format of redundant binary number during partial productsaccumulation stage.Finally,an RB-NB converter is used to convert the redundant binary product tonormal binary product.Due to the fact that all structures in normal binary adder can be applied toRB-NB converter,a high-performance parallel-prefix/carry-select strucutre is introduced to constructthe RB-NB converter after analyzing conventional parallel prefix adders.In this structure,conventionalSklansky parallel prefix structure is optimized,which effectively reduces the delay caused by theincrease of fanout.Meanwhile,a “plus one” circuit fit for RB-NB converter is employed in carry-selectstructure to reduce area.This thesis completes series of work as follows: design of whole structure, algorithms’ research,coding, simulation and synthesis. All designs are described with Verilog HDL and synthesized onSynopsys Design Compiler. Synthezied results show that the design of redundant binary multiplierachieves expected targets.At the end,a layout for this redundant binary multiplier implemented onAstro is given.