New Pipeline Adc System Modeling And Optimization Method

To satisfy the increasing need for ADC performance set by High Definition Audio and Video Signal Processing and Wireless Communication systems, systematic modeling and optimizing method for new High-Speed High-Resolution (HSHR) Pipeline ADC is investigated. This high performance system is elaborated and modeled, followed by simulation and optimization of systematic performance metrics, which yields the method to assign core specifications to components.Based on the selected Pipeline ADC architecture, key characters such as speed and resolution are modeled and optimized. Abstractly modeling speed, noise and power in Pipeline ADC, the first group of core parameters are designed to achieve the optimized compromise of speed, noise and power. These parameters are stage-resolution (3.5+1.5x7+2) assignments and capacitor scaling factor assignments for optimization.Afterwards, using these parameters specified by combined constraints from noise, speed and power, further design of core systematic parameters is completed with modeling the system linearity, which realizes new HSHR performances. By modeling abstract expressions for kernel modules in system level, sources that determine system linearity are found to be quantization, finite open-loop gain of OTA in MDAC, capacitor mismatch, Temperature coefficient (Tempco) and line regulation. Core metrics including SFDR, INL and DNL are investigated and are shown with their relations to quantization and circuit non-idealities. The corresponding method for circuit specifications assignment is presented. Especially, the connection provided by modeling INL versus non-linearity and modeling SFDR versus INL is effectively used to bridge the vital relations between SFDR and non-linearity sources.In Matlab environment, incorporating these metrics modeling, the Pipeline ADC linearity and resolution is simulated and optimized with designed resolution of 12 and sampling frequency f_sampling of 100Msps. Simulation results indicate when frequency of input signal is 49.72MHz, and when OTA open-loop gain error and capacitor mismatch models are both employed, f_u more than 1.77GHz with A_v more than 84.2dB for OTA, A_c0 more than 500μm² for capacitor, Tempco of 8.93ppm/℃and line regulation of 1860ppm/V should all be satisfied for practical ADC, if SFDR more than 80dB, DNL less than 0.5LSB, a settling resolution, allowed by 12bit/100Msps Pipeline ADC, and ENOB more than 11.98 bit are simultaneously desired.Results show that through this systematic modeling and optimizing systematic behavior of 12bit/100Msps ADC can be effectively realized, with rational circuit specifications assignment presented, facilitating modern high data throughput signal-processing systems such as Wireless Communications.