High Performance SDRAM Controller Design And Verification With Software

With consumer electronics product features increased, the amount of memory required for the products is also growing. In consumer electronics, portable electronics market has gradually become the main product which requires that battery life is also increasing, so the system requirements for low power consumption are becoming increasingly intense. With the system on chip(SoC) continue to expand in the field of embedded system applications, system performance requirements are also increasing. In today’s increasing chip speed, slow memory access has become an important bottleneck in overall system performance improvement. Therefore, the design can support a large-capacity SDRAM, high performance while taking into account the power consumption of the entire system memory controller has a very important significance.This paper first analyzes the basic principles and architecture of SDRAM, the chip interface defined by JEDEC specification, and SDRAM basic operation and timing control. Based on the functions and features of LPDDR2/DDR3 SDRAM devices and system requirements for memory storage, this paper discusses the implementation of a multiple port bus access control logic integrated memory controller and the FPGA-based hardware and software co-verification.For the design of the controller, in order to improve the performance of the memory controller, the device is designed to support SDRAM open page and close page access mode, the system can base on the address range features of SDRAM access to choose which access mode using. Also for performance considerations, the internal controller also integrates an arbitration mechanism and the design of several priority selection mechanisms.In order to consider the power consumption of the entire system, the controller supports SDRAM device into suspend mode. After the system into suspend mode system can be powered down to maximumly reduce the power dissipation. In normal operation mode, if the controller detects that there is not access to memory, controller will pull the clock enable signal to low state so let SDRAM device into a low power state.This paper discusses the functional verification of code level, DC synthesis and FPGA-based verification to completely verificate the controller. During FPGA verification the SDRAM controller is integrated into the ARM core SoC system to simulate the controller’s real working environment, using C language to generate test procedures, test the controller with arge amounts of data acess, and also test various operating processes of SDRAM controller. Through the combination of hardware and software to more realisitically verify the correctness and stability of the controller.