Low Power SDRAM Controller Design And Verification With Software

With the development of digital IC design methodology, the requirement for electronic products is also increasing. On the one hand, with the scale’s increasing of integrated circuits, more and more functions are integrated in a single system, so the performance of memory storage are also increasing. On the other hand, with the popular usage and application of portable products, power consumption has become an important factor for chip design considerations, and sometimes even a decisive factor for the success of a product.Firstly, the types of SDRAM, the structure and operation methodology of SDRAM are briefly introduced in this paper. One type of SDRAM controller combined with clock-gating architecture and command reordering architecture is proposed in this paper(Gated clock structure can reduce the power consumption of clock tree from the clock root and can reduce the dynamic power consumption of registers. The command reordering architecture can put the SDRAM commands whose address are in the same bank as well as in the same page/row together to saving the duration of row’s ACTIVE and PRECHARGE operation, put the SDRAM commands whose address are in the same bank but not in the same page/row separated to ensure that each banks can be operated concurrently, thereby the efficiency and bandwidth of SDRAM accessing can be increased). Gated-clock and command reordering architecture can make the SDRAM controller to achieve high performance SDRAM accessing with little effect on power consumption.Verilog hardware description language is used to design the SDRAM controller described before. After the design, the following steps are described in this paper: Dynamic simulation using the OVM(a advanced verification methodology based System Verilog) is used to verify the function of SDRAM controller; Synthesis using Synopsys’ s Design Compiler is used to ensure that the design can be synthesized normally;Formal verification using Cadence’s LEC is used to ensure the correctness of netlist’s function; Power analyzing using Synopsys’ s Primetime PX is used to analyze the power consumption in different operation mode. Finally, the conclusions are described in this paper.The design after verification proves that the power consumption and performance are superior compared with the SDRAM controller dose not use the gated clock technique and command reordering technique. Both power consumption and performance of this SDRAM controller can satisfy the basic requirement for our company’s low-end DVD product, so in the future, this SDRAM controller is likely to apply to the DVD product or other low-end product in our company, this is one of the contribution to our company through this subject. Clock gating technique and the power analysis methods proposed in this paper can also play a certain reference role for low-power IP or IC in the future.