Design And Verification Of DDR3SDRAM Controller

Compared with the previous generation，the new generation of DDR3SDRAM memoryhas a larger capacity and a better capability.Therefore，it is widely used in the filed of digitalsystem，especially in the SoC system. This thesis aims to do some research in the strategy ofraising the utilization ratio of the DDR3controller，expanding the multi-interfaces of theAMBA BUS and designing the concrete applications of multilevel arbitration mechanism.To begin with，the writer extracted，on the basis of standard JEDEC STANDARD DDR3SDRAM Specification， some important parameters that may affect the function andperformance of the design.Then，the writer designed the time sequence which is strictly inaccordance with those parameters and divided the detailed design into several submodulesaccording to the overall design frame diagram. After defining the function and interfacesignals of each submodules，the writer finished the description of the verilog HDL hardwarelanguage of these submodules.Secondly，in respect of utilization ratio of the bandwidth， the writer proposed that theinterleave of reading and writing command should be activated and command should be shutdown in order to fully raise the utilization ratio of the DDR3data bus.If there is nocommand of the state machine that is in the same bank or the same row with the commandbeing issued，the last command issued will be WRA/RDA. The internal state machine will becompletely streamy operated and two successive command will be completely andsuccessively executed.In the next place，the writer designed the expandable bus interface which has applicationin the SoC system. Each master interface is able to have read-write data access to the DDR3sdram. The master interface is connected through the AXI bus and the multilevel arbitrationmechanism is applied in this desig. Timeout has the highest priority level.The priority attribute of command has the second priority and the port numbers of AXIbus has the third priority level.At the end of the thesis，the writer verified the functions of the controller designed. All the functions can completely meet the protocol standard of JEDEC STANDARD DDR3SDRAM SPECIFICATION. The time sequence is regular and the controller is able to havenormal read-write access to the data in DDR3sdram memory.In respect of its performance，this design is available to be applied on SoC system and the frequency is able to reach800MHz. The strategy of improving bandwidth quoted meet the actual need of the SoC system.