The Research Of Aging Tolerance Methodology For Digital Integrated Circuit

The shrinking silicon feature size and the rapid development of microelectronics technology seriously affected the reliability of digital integrated circuit. Aging effect due to NBTI (Negative Bias Temperature Instability) can decrease the lifetime and cause the performances degradation of the digital integrated circuit. The research of aging tolerance methodology has become an extremely critical work to certain the reliability of digital integrated circuit. This thesis focus on the research of aging tolerance relevant methodology to ensure the reliability of integrated circuit and the major works in this thesis are listed as follows.1. The aging effect which influents the lifetime of the digital integrated circuit is introduced in detail. And then the induced-mechanism, mathematical model and the mitigation methods of the aging effect are stated. Moreover, some typical existing methods mitigating the circuit aging effect during the sleep time are recommended and their advantages and deficiencies are analyzed.2. This thesis proposes a time-efficient critical gates identification method with topological connection analysis, which chooses a small set of critical gates. The proposed scheme could overcome the limitation that the conventional aging critical gates identification method requires an undesirable CPU runtime and also results in the circuit over-protected. Experimental results over many circuits of ITC99 and ISCAS benchmark demonstrate that, to guarantee the normal lifetime (e.g.10 years) of each circuit, it achieves a 3.97x speedup and saves as much as 27.21% area overhead compared to the existing method.3. An aging masking unit based on the switch features of the transistor is designed in this thesis. It can efficiently decrease the larger transmission pull delay of the aging critical gates and the critical paths’delay during the active time could be reduced in digital integrated circuit. As critical paths meet the timing constraint, the circuit could be protected from aging and do not experience the circuit failure danger.