Research On Aging Failure Prediction And Protection For The Digital Circuits

The aggressive scaling down technology has largely improved the performance of digital circuits. However, it has brought more challenges to the reliability of circuits in nanometer technology, one of which is the effect of circuit aging. The circuit aging would increase the transistor threshed voltage, decrease the speed of gate, increase the circuit delay, cause the timing violation and eventually lead to the circuit failure. Previous works show that the aging would lead to a20%degradation of circuit performance in10years.This dissertation focuses on the aging failure prediction and protection of digital circuits and introduces the related methods to solve the problems caused by circuit aging. The main contributions of the dissertation are as follows:(1) The Critical Path Selecting of Digital Circuits based on Transition Probability of Signal. In the digital circuits, the aging process of each data path is difference with each other. The timing violation only occurs in some critical data path under the influence of circuit aging. The previous woks could not scale the set of critical path effectively. A critical path selecting method is introduced in this work. In the circuits, each type of gate has its own signal transition probability, so that the duty cycles of them are different from each other. This selecting method makes use of the signal transition probability to compute the duty cycle of workload on data path, base on which the variation of circuit delay during the whole process of circuit aging is described as well. And finally, according to the aging delay of data path, the set of critical path is generated. The experiment results show that the proposed delay computing method could describe the variation of circuit delay precisely the change of circuit delay, and the critical path selecting method could reduce the set of critical path effectively.(2) The Aging Failure Prediction for Digital Circuits using Double Triggered Pattern. In circuit level, the feather of aging is the increasing of circuit delay on data path. The online testing of circuits could effectively prediction the failure caused by circuit aging. The critical technology of online failure prediction is the optimized design of aging sensor. An online aging failure prediction method using double triggered pattern is proposed in this dissertation. Based on the analysis of aging feathers, this method employs the double-edge-triggered flip-flop to sample the signal of the circuits, and it use signal of the combinational logic to control the sampling process of aging sensor. The detection interval is generated by the setup time of different flip-flops, which is used to predict whether the error caused by circuit aging would occur. The experiment results show that this method would effectively predict the circuit failure, the influence of process variation on the proposed method is low, and it also make a low area, power and performance cost of circuits.(3) The In-field Circuit Aging Measurement using Self-oscillation Loops. The precise measurement of circuit aging is critical to the implement of specific aging protection method. The traditional aging measurement method could not compute the aging process effectively. In this dissertation, an aging measurement method using self-oscillation loops is presented. This method selects critical path from circuits; keeps the odd times of inverters on the path and construct the self-oscillation loops by the interior devices of the critical path; reuses the mechanism of built-in self test to generate the testing patterns and agitate the self-oscillation loops; employs the aging signature counter to quantify aging feature and measure the aging process. The simulation results show that the measurement precise of proposed method is more than90%, and the method is resilient to the effect of process variation.(4) The Aging Failure Protection for Digital Circuits using Time-Space Redundancy. The motivation of aging resilient is to protect the digital circuits from failure. The traditional circuit protection methods would permanently modify the structure and the performance of circuits. In this dissertation, an aging protection mechanism using time-space redundancy is proposed. This mechanism employs the redundant space cells to realize the self-detection process of circuits, and employ multi-timing signals to correct the error caused by circuit aging. After each time of error correction, the protection mechanism would make use of self-adaptive clock scaling cell to shift the clock difference, in order to keep the consistency of all the clock of circuits. The experiments show that this protection would improve the Mean Time-to-Failure by2%,23%,116%, and232%with the clock difference of5%,10%,20%, and25%.