A Background Calibration Algorithm Of Time-Interleaved ADC

Nowadays, digital signal processing technology has become one of the most important technologies for signal processing, and is widely used in many important areas such as communication, radar, medical equipment, speech recognition. As an electronic component, converting analog signals into digital signals, Analog-to-Digital Converter (ADC) plays a more and more important role with the rapid development of digital technology. However, the contradictory relationship between speed and accuracy severely restricts the performance of ADC.Time-interleaved ADC (TIADC) architecture becomes an important choice to breakthrough bottleneck. It adopts a structure with multiple channels, sampling alternatively and parallelly. This structure maintains the conversion accuracy of sub-channel ADC, while doubling the overall ADC sampling rate. Unfortunately, the fabrication error of TIADC leads to offset mismatch, gain mismatch and clock mismatch among the channels. The mismatch errors severely restrict the dynamic performance of TIADC systems. Digital calibration technique has become the key technologies to improve the performance of TIADC oFirstly, this thesis establishes an equivalent system error model for the three basic mismatches based on the work principle of the TIADC. This thesis also analyzes their impact to the system performance theoretically and provides the applied range of the existing calibration algorithm.Next, this thesis designs a fully digital background calibration algorithm based on LMS adaptive filtering for the three mismatch errors. The algorithm calibrates the gain mismatch and clock mismatch errors via the improved variable step LMS adaptive filter, improving the convergence rate of the adaptive process. The offset mismatch is eliminated by exponential average accumulates.In order to verify the effectiveness of the algorithm, this thesis establishes a TIADC model with 5 channels in the Matlab/Simulink, based on a sub-channel consisting of a Pipeline ADC, whose precision is 10bit and whose sampling rate is 200MHz. Then this thesis completes functional design and verification for the algorithms. Furthermore, the simulation of the Verilog HDL coding of the algorithm is done in Modelsim, and the performance of the calibration algorithm is measured via the experiments on the FPGA platform. The results indicate that the algorithm can achieve a good performance and it can improve the ENOB of the system from 3.31562 to 9.33113, and improve the SNR from 21.7221dB to 57.953dB.