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Design Of VGA And Research Of TIADC Signal Calibration For UWB Communication System

Posted on:2010-03-25Degree:MasterType:Thesis
Country:ChinaCandidate:B Y LinFull Text:PDF
GTID:2178360302959721Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Ultra-wideband communication system is a new communication system which has a very high bandwidth occupation. It has the advantage of high-speed data transfer rate comparing to the traditional wireless transmission technology that can not match.In the mobile wireless communication signal transmission channel there is the issue of timing variation, so the signal obtained by the receiver's antenna doesn't has a fixed amplitude. Thus we need to design the automated gain control (Automated Gain Control, AGC) circuit in order to stabilize the amplitude of the input signal. This paper analyzes the active inductor in enhancing the role of system bandwidth, using the pseudo-exponential function to realize the linear-dB feature. And in order to cancel the DC offset caused by the zero-IF receiving topology, an extra feed-back circuit is also added in. Plus the input/output match circuit is also adopted for the test reason. And finally a high-frequency with a 3dB bandwidth of 1GHz VGA is designed. The highest gain of this design is 36.99dB while the minimum gain is 1.72dB. The dynamic gain range of the VGA system is 35.27dB.The UWB wireless transmission of ultra-high speed puts great pressure on the back-end design of high-speed ADC. This paper discusses the system integrated solution of the Time Interleaved ADC (TIADC). A new TIADC system suitable for the digital-background measurement and calibration of these errors is proposed in this paper. Also, a fast interpolation algorithm aimed at the real time calibration of timing mismatch is discussed in great detail. The algorithm is easy to be implemented on chip. Simulation results show that the proposed system architecture and the algorithm can improve the spurious free dynamic range (SFDR) due to timing-error mismatch of the TIADC significantly with 41.42dB, providing an online mismatch error correction for high-speed TIADC.
Keywords/Search Tags:UWB, CMOS, VGA, TIADC, Digital Background Calibration, Timing Mismatch, Fast Interpolation
PDF Full Text Request
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