Tiadc System Clock Mismatch Fmc Calibration Algorithm And The Fpga Implementation

The analog-to-digital converter (ADC) is a critical component in modern digitalcommunication. However, as communication bandwidths increase, the availability ofADCs with sufficient speed as well as high resolution becomes a concern. As we know,it is difficult to improve the ADC’s speed and accuracy at the same time, we must keepthe balance between speed and resolution. Well, Time-Interleaves ADC (TIADC) canimprove the speed of sampling rate by its parallel structure, this feature has prompted agreat interest in TIADCs. However, due to manufacturing limitations, mismatch errorsare created, such as gain mismatch, offset mismatch and time mismatch, which leads tothe degradation of TIADC’s performance. So, it is necessary to make a study ofcalibration technology to compensate the loss of TIADC’s performance.At first, this paper analyzes the effects of channel mismatches on the TIADC’sdynamic performance through deriving mathematical formula. In-depth studies of timemismatch are conducted, a taylor series approximated time mismatch model isestablished for time mismatch calibration, and the availability of the approximationmodel is verified.Then, an blind adaptive time mismatch calibration algorithm based on theapproximation model is proposed, simulation results suggest it works well. Consideringthe blind calibration has flaws, an adaptive calibration based on test signal method isproposed, MATLAB simulation suggests ENOB of the4-channel12-bit TIADC isincreased by5.5bits and SFDR by37dB.Finally, clock calibration circuits for4-channel12-bit TIADCs are designed andimplemented based on ALTERA STRATIX III series FPGA, using pipeline optimizationalgorithm to meet the speed requirements. Circuit implementation results and testresults show that the calibration method which the paper proposed can improve theTIADC’s performance effectively, ENOB is increased by5bits and SFDR by35dB.