Adaptive Tiadc Error Calibration Algorithm And Its Fpga Implementation

The performance of today’s digital system is highly dependent on the employedanalog-to-digital converters (ADC), and in order to acquire high speed, highperformance digital system, high-performance ADC is required. In this regard,time-interleaved analog to digital converter (TIADC) can be a reasonable solution.However, the performance is degraded by offset mismatches, gain mismatches, andsample-time errors between the sub-ADCs. The digital calibration techniques becomethe key technology to improve the performance of TIADC.Firstly,on the basis of existing research,an error TIADC model based on filter bankis established.This paper analyzes channel mismatch,which include offsetmismatch,gain mismatch and sample-time mismatch, effects in TIADC and summarizethe existing calibration technology.Then, an adaptive offset mismatch and gain mismatch calibration algorithm ispresented. This algorithm is based on the equality of channel mean and channel energy.Simulation results show that this algorithm can accurately estimate DC offset mismatchand gain mismatch and can eliminate the effects of these two kinds of errors.Thirdly, this paper proposes a parametric polyphase filter bank to calibratesample-time error. This method requires the input signal to have a significantly richspectrum and be slightly oversampled. A4-channel12-bit TIADC system is simulatedwith SFDR improved by32.35dB.Finally, a mismatch calibration circuit for4-channel12-bit TIADCs isimplemented based on FPGA.The circuit uses less resources and has goog performance.Test results show that the SFDR after calibration is over70dB.