Study On The Calibration Of Ti-adc Mismatch Based On Reference Channel

As a bridge between analog domain and digital domain,analog-to-digital converter is widely used in many fields,But as result of the limitation of technology,the traditional single ADC has been unable to meet the requirements of high accuracy and high speed in practical application,while time-interleaved analog-to-digital converter?time-interleaved ADC,TIADC?achieve the goal of high speed and precision by using multiple ADC parallel sampling operations,which become a hot spot of research and application in the domain of ADC.Due to the influence of manufacturing process and environmental factors,the mismatch error occurred in each sub-channel of TIADC greatly reduced the performance of the system.In this thesis,three adaptive calibration algorithms based on reference channel were designed to eliminate the influence of offset,gain and time mismatch respectively.Two calibration algorithms based on statistical principle are designed to calibrate offset and gain mismatch.In view of the time mismatch,which is admittedly difficult to calibrate,first of all,the thesis analyzed two main problems about low accuracy and the limitation of input signal bandwidth,which are existed in many estimation algorithms,and then designed a estimation algorithm based on polarity judgment.This algorithm improved the algorithm structure according to the problems above,improved the accuracy of the estimation results,and expand the bandwidth to the system Nyquist frequency,finally,the error compensation is realized by Taylor series expansion.The mismatch estimation module and compensation module form the calibration loop and realized the self-adaptive calibration of time mismatch.In order to verify the function of the algorithm,a 12Bits-0.4GHz four-channel TIADC model was built based on the MATLAB/Simulink,when the normalized frequency was f_in/f_s=0.45,the ENOB increase from 4.54Bits to 11.75Bits and SNR increase from 29.08dB to 72.52dB.Circuit verification was carried out on FPGA,and ENOB increased to 11.70Bits,SNR increased to 72.25dB,and the verification results proved the validity of the algorithm.