Design And Implementation Of Blind Background Calibration Algorithm For TIADC Mismatch Based On Least Mean Square

With the development of digital technology,digital to analog converter(ADC)has been widely used in communication,computer and instrument control and other fields.The multi-channel time interleaving(TI)structure can improve the sampling rate and resolution of ADCs,but the offset,gain and time skew mismatch seriously limit the performance of TIADC.However,there is a contradiction between the convergence speed and accuracy of the fixed step calibration algorithm.Therefore,it is necessary to study the calibration algorithm based on variable step size.In this thesis,the effect of step size on the accuracy and convergence rate is analyzed and simulated.When the step size is large,the mismatch can be quickly calibrated,but the steady-state accuracy is low.Oppositely,the algorithm converges slowly,but the steady-state accuracy is better.Therefore,this thesis adopts G-SVSLMS variable step algorithm to accelerate the convergence speed under the premise of ensuring the accuracy of the algorithm.In this thesis,the G-SVSLMS algorithm is firstly improved.Secondly,the influence of the two parameters of the G-SVSLMS algorithm on the accuracy and speed of mismatch calibration is analyzed and simulated,and the direction of parameter optimization is clarified.Because both parameters will affect the accuracy and convergence rate of the algorithm,this is a multivariate nonlinear problem.In this thesis,the range of solution sets of and parameters is determined according to the size of mismatch,and the optimum coefficient is obtained by using simulated annealing algorithm.In terms of hardware implementation,the RTL code of the algorithm is designed and tested based on FPGA.In this thesis,a 4-channel 14 bits TIADC PCB was used to verify and test the improved G-SVSLMS algorithm.The data before and after calibration showed that when the input frequency was 103.34MHz,SFDR increased from 49.59dB to 73.09 dB,SNDR increased from 37.28 dB to 61.37 dB.In terms of the convergence speed of the algorithm,compared with the fixed-step algorithm,the modified variable step algorithm in this thesis reduces iteration points from 4×10~6 points to 2.89×10~5 points,greatly accelerating the convergence speed of the algorithm.