The Research And Design Of The High Speed Data Transmission System Based On USB 3.0

Data transmission systems play an important role in a large number of electronic equipments,which have widely application in many areas such as data acquisition, industrial control,and testing. Various data transmission systems have been developed and researched in and abroad, in which PCI(Peripheral Component Interconnect) or USB 2.0(Universal Serial Bus) is usually used as interface. PCI is not as convenient as USB when used, while USB 2.0 is limited of the bandwidth of 480 MHz to realize ultra high speed data transmission. In contrast, USB 3.0’s transmission rates reach to 5Gbps and the limitation of bandwidth in USB2.0 is efficiently solved. The high speed data transmission systems combine the usability of USB and the need for high transmission rate, and the research to such systems has realistic significance.A data transmission system’s design scheme based on FPGA(Field Programmable Gate Array) and USB3.0 is presented and realizedin the thesis, and the following aspects are proposed.1. The technique of FPGA and the characteristic of USB3.0 protocol are elaborated. CYUSB3014, which is in common market, has been chosen as the USB3.0 surface in the research, though considering many important aspects, such as inner resources of the surface chips,protocol support, technical support,application universality and development cost.The general frame to the high speed data transmission system has been designed based on CYUSB3014.2. The general system hardware design has been presented, and the circuit schematics for concrete modules have been illuminated. The principle of place and route followed in the system PCB(Printed Circuit Board) design bas been illustrated based on the problem encountered in high speed PCB design combined with PCB design specifications of FX3.3. The hierarchical way has been adopted in logic design, which is divided into the data acquisition part and the data transmission part including sequential proceeding layer and transaction layer. In the sequential proceeding layer, the three state sending and receiving state in interactional cycling machine has been designed based on the characteristic of CYUSB3014’s Slave FIFO(First Input First Output) surface. In the transaction layer, sending and receiving modules have been designed to take charge for the resolution, storage, receiving, package and relative scheduling of user-defined packets. The problem of cross clock domain has been specially handled.4. System software has been designed,which include three parts:based on firmware reference provided by Cypress,the firmware program have been designed for the adaption of the logical design; the Cypress’ s device drivers have been modified for the actual need in this system; the applications for chip’s data acquisition and testing have been written.5. The system hardware and software have been debugged. The system acquisition data is compared with acquisition data in the logic analyzer and the acquisition rate is calculated. Results indicate that the system satisfies design requirement.