The Design And Realization Of Digital Frequency Multiplier Using FPGA/CPLD

The rapid development of modern electronic test system has raised an advanced requirement for all-digital frequency. Indexes including the output frequency stability, frequency tracking speed, output frequency range as well as output frequency points should meet higher requirements, thus the need of research for high-performance all-digital frequency multiplier is very urgent. Embedded all-digital frequency multiplier design has become a necessity because of the application of concurrent engineering. The quality of digital frequency multiplier is one of the most important factors that impact the test system.To solve the mentioned problem and based on the digital frequency used in components detection system, this paper is aimed to analyze the error-causes of digital frequency multiplier and make a research about the way and theory of how to overcome it. By doing experiments and tests, the designed all-digital frequency multiplier with adaptive functions is up to standard with ideal performance indexes. The steps are as follows:(1)Causes of errors ordinary digital frequency multipliers and all-digital frequency multipliers make are analyzed, as well as a research of how to overcome them. By doing that, it is possible to put forward an error compensation with adaptive functions and related algorithm of how to realize it. Thus the theoretical foundation for system design is laid. According to the tasks, the main performance indexes are made for the frequency multiplier.(2)The paper studies interface design of man-machine interaction and system design of all-digital frequency multiplier with adaptive functions. The man-machine interaction interface circuit and all-digital frequency multiplier with adaptive functions can be achieved in one FPGA chip through the appropriate choice of FPGA chip and HDL, which is the hardware description language.(3)The paper includes the test solution for digital frequency multiplier which some related tests are made. In order to improve reliability of this design, all the function module tests adopts Quartus+Ⅱfor simulation technique. The results of the design are downloaded to FPGA, the carrier chip, after confirmation of the accuracy of those function module tests. This paper also involves a test plan which aims to trace velocity and precision, the main indexes of digital frequency multiplier.According to analysis about the problems found in the tests, self-compensating digital frequency multiplier has defect itself. When the system is stable, self-compensating digital frequency multiplier is reliable. However, significant descend of its precision can be seen if input signal cycle of all-digital frequency multiplier changes greatly, thus leads to ‘swallow pulse’ and ‘spit pulse’.