.1.244 Ghz 0.25mm Cmos Process Variable Sub-frequency Phase-locked Loop Frequency Multiplier Design,

With the rapid development of telecommunication networks, computer networks and Internet, it is urgent to build information super-highway. Optic-fiber communication systems are the principal parts of information super-highway for its merits such as great capacity, long transmit distance, economizing energy source, anti interference and anti radiation etc. VSR (Very Short Reach) has offered a kind of low-cost short distance, large capacity interconnected way for network operator as one kind of fiber optic communication, so have extremely wide market prospects. A monolithic clock synthesis PLL, which is expected to apply to VSR system, has been designed and characterized in this paper. The PLL consists of a ring oscillator, a frequency divider, a phase/frequency detector, a charge pump and a loop filter. The factor of the frequency divider is programmable. All cells have differential architecture.At the moment, most of RF chips and ultra high-speed circuits are based on technologies such as GaAs, Bipolar Si, BiCMOS and so on. With the development toward sub-micron and deep sub-micron technologies, CMOS will take more and more important role in the field of RF IC and ultra high-speed IC design because it's low cost and easy of implementation. Hence the frequency synthesizer has been designed in TSMC 0.25 μm CMOS technology.This paper introduces the design processes and final test results of above-mentioned circuit in detail according to the order of circuit design, layout design, process to test. All circuit undergoes simulation, accord with the design requirement, and the layouts have been delivered to the chip manufacturer and successfully fabricated. The measure results of the chipset validate our design specifications.