A CDR with a digital threshold decision technique and a cyclic reference injected DLL frequency multiplier with a period error compensation loop

This dissertation proposes a CDR with a digital-threshold decision technique which enables high jitter tolerance performance, fast acquisition, low complexity and low power consumption, and a cyclic reference-injected, programmable DLL based frequency multiplier with a novel period error compensation loop to reduce the output spur as well as with a new switching scheme to avoid harmonic locking without initialization or extra locking detection circuitry.; First, the recently reported CDR circuits and DLL based frequency multipliers are reviewed according to the given classification. Performances are compared against each type of CDR or DLL frequency multiplier, and the advantages and disadvantages are discussed.; Then the proposed digital threshold decision technique and the CDR circuit implementation as well as the measured results are presented. The digital threshold decision technique in the general cases is first given, and with the chosen parameters, the CDR with the proposed technique is followed. The CDR functionality is verified with Matlab model simulation, and an event-driven simulation verifies the high jitter tolerance performance of the proposed CDR decision technique. The CDR was implemented in CMOS 90nm technology with new circuit ideas to reduce the circuit complexity and the power consumption. The total transistor count of the CDR excluding the output buffers is approximately 900. With the input data from an on-chip 7-bit PRBS data generator and the sampling clocks from an on-chip DLL multi-phase clock generator, the CDR circuit was measured with an on-chip BER test circuit, and the expected correct phase tracking was observed from 2.0Gbps to 3.5Gbps. By measuring the maximum difference between the baud rate and the sampling clock rate, the jitter tolerance performance obtained from the measurements is close to the theoretically analyzed one, which is well comparable or even better than the reported ones. The measured power consumption of the core CDR circuit is 4mW at 2.5Gbps and 5.3mW at 3.0Gbps at a 1.2V power supply. All these verify the proposed CDR with the digital threshold decision technique and its CMOS implementation.; In the DLL based frequency multiplier design, the in-lock error from all error sources including the re-alignment error caused by the cyclic reference edge injection contributes to the spurious power level. So a low-bandwidth auxiliary loop, which was first verified in Matlab model simulation, is employed to compensate the output period error caused by the in-lock errors from various sources for spurious power reduction. By employing a novel switching control scheme, the circuit is capable of locking to frequencies either above or below the start-up frequency without initialization. With a dynamic frequency divider, programmable multiplication ratios from 13 to 20 are achieved with an output frequency range of 900MHz to 2.9GHz. The circuit was implemented in TSMC 0.18mum CMOS technology and measured with the reference from an RF generator, and the measured results show a significant output spur improvement from -23dB to -46.5dB at 1.216GHz. The measured cycle-to-cycle timing jitter at 2.16GHz is 1.6ps (rms) and 12.9ps (peak-to-peak), and the phase noise is -110dBc/Hz at 100kHz offset with a power consumption of 19.8mW at a 1.8V power supply. The measurements also verify the proposed period error compensation method as well as the new switching scheme and their transistor-level implementation.