Frequency Divider And Automatic Frequency Calibration For 5G Millimeter-wave Applications

As an important device in 5G wireless system,frequency synthesizer(FS)can not only work as a stable local oscillator for the communication system,but also provide accurate clock signals.To meet the requirements of FS working in the 5G millimeter-wave band,this thesis focuses on the frequency divider and automatic frequency calibration structure.This thesis first discusses the frequency synthesizer,based on the performance requirements of the phase-locked loop,selects the charge pump phase-locked loop,discusses its working principle,analyzes the linearization model,obtains the noise model,and then determines the loop parameters based on the maximum phase margin method,finally determines the specific structure of the phase-locked loop frequency synthesizer.The frequency division link is realized by a cascaded structure of analog and digital frequency dividers,which reduces the chip power consumption and chip area.Then the prescaler based on injection-locked is discussed,the working principle of the injection-locked frequency divider is introduced,and two prescalers are designed.The source of the injection transistor of the divide by three frequency divider structure is directly connected to the gate of the cross-coupled transistor,which improves the injection efficiency and enlarges the locking range.The active and passive components involved in the prescaler are discussed in detail,the parameters of each module are determined,and the layout and design results of the prescaler are given.Then classify the digital frequency divider,analyze and discuss the advantages and disadvantages of the current mode logic and the true-single-phase-clock divider,design a differential divide by 4 frequency divider based on current mode logic and the single-ended divide by 16 frequency divider based on true-single-phase-clock,and give the test plan and result of the chip.In addition,A dual-mode frequency divider that integrates the gate circuit into the frequency divider circuit is also designed,which increases the maximum operating frequency of the frequency divider circuit,reduces the power consumption of the frequency divider circuit,and gives the layout and design results.Finally,an automatic frequency calibration structure using a 2-point search algorithm is designed,which speeds up the search for the VCO subband and reduces the lock time of the phase-locked loop.By writing Verilog code,an automatic frequency calibration structure is designed.This thesis uses 0.18um CMOS technology to design a frequency divider and automatic frequency calibration structure that works in the 5G millimeter-wave frequency band,and tape out some of the devices.The test results show that the self-resonant frequency of the current mode logic structure divided by 4 is 2.056GHz,the frequency division range covers at least4.8GHz-10GHz,the total power consumption under 1.2V power supply voltage is 7.6m W,and the core area of the chip is 0.24×0.14 mm~2.The self-resonant frequency of the true-single-phase-clock divided by 16 is 92MHz,the highest operating frequency is 2.2GHz,the core area is 0.4×0.06mm~2,and the power consumption is 2.4m W.When the designed 5G millimeter-wave frequency divider is injected with 0d Bm signal amplitude,the locking range is24-30GHz,and the chip area is 0.9×0.8mm~2.Based on the 2-point search algorithm,an automatic frequency calibration structure is designed,and the calibration time is within 16us.